kernel/arch/riscv64/vcpu/
mod.rs1use super::{Registers, Riscv64};
8
9#[derive(Debug, Clone, Copy, PartialEq)]
10pub enum Mode {
11 User,
12 Kernel,
13}
14
15#[derive(Debug, Clone)]
16pub struct Vcpu {
17 pub regs: Registers,
18 pc: u64,
19 asid: usize,
20 mode: Mode,
21}
22
23impl Vcpu {
24 pub fn new(mode: Mode) -> Self {
25 Vcpu {
26 regs: Registers::new(),
27 pc: 0,
28 asid: 0,
29 mode,
30 }
31 }
32
33 pub fn set_asid(&mut self, asid: usize) {
34 self.asid = asid;
35 }
36
37 pub fn set_pc(&mut self, pc: u64) {
38 self.pc = pc;
39 }
40
41 pub fn get_pc(&self) -> u64 {
42 self.pc
43 }
44
45 pub fn set_sp(&mut self, sp: usize) {
46 self.regs.reg[2] = sp;
47 }
48
49 pub fn get_mode(&self) -> Mode {
50 self.mode
51 }
52
53 pub fn store(&mut self, riscv64: &Riscv64) {
54 self.regs = riscv64.regs;
55 self.pc = riscv64.epc;
56 }
57
58 pub fn switch(&mut self, riscv64: &mut Riscv64) {
59 riscv64.regs = self.regs;
60 riscv64.epc = self.pc;
61 }
62}