Module plic

RISC-V Platform-Level Interrupt Controller (PLIC) Implementation

The PLIC is responsible for managing external interrupts from devices and routing them to different CPUs with priority support.

Structs

Plic

RISC-V PLIC Implementation

Constants

MAX_CPUS 🔒

Maximum number of CPUs supported by this PLIC implementation

MAX_INTERRUPTS 🔒

Maximum number of interrupts supported by this PLIC implementation

PLIC_CLAIM_BASE 🔒

PLIC_CONTEXT_STRIDE 🔒

PLIC context stride for threshold/claim registers (per context)

PLIC_ENABLE_BASE 🔒

PLIC_ENABLE_CONTEXT_STRIDE 🔒

PLIC context stride for enable registers (per context)

PLIC_PENDING_BASE 🔒

PLIC_PRIORITY_BASE 🔒

PLIC register offsets

PLIC_THRESHOLD_BASE 🔒

Statics

__EARLY_INITCALL__ 🔒

Functions

probe_fn 🔒

register_driver 🔒

remove_fn 🔒